1. Field
The described embodiments relate to computer systems. More specifically, the described embodiments relate to techniques for issuing instructions with unresolved data dependencies.
2. Related Art
Some modern microprocessors are “in-order” processors that issue instructions for execution in program order. These in-order processors typically include an issue unit that manages instruction issue as part of the enforcement of program ordering. In most of these processors, the issue unit includes a scoreboard mechanism for keeping track of dependencies between instructions in the processor. Generally, for each instruction being executed in the processor, the scoreboard holds a record that includes information about the instruction (e.g., a destination register identifier and other attributes) that the processor can use to determine when an instruction should be issued relative to other instructions.
In many of these processors, the issue unit can use a record in the scoreboard to delay the issuance of a given instruction until a prior instruction has had a chance to produce a result. In other words, the issue unit may stall the issuance of an instruction by holding the instruction at the head of a first-in-first-out issue queue until a prior instruction (upon which the instruction depends) has had a chance to output a value into its destination register. For instructions that interact with off-processor devices (e.g., a memory system or an I/O device), these delays can be dozens or even hundreds of processor clock cycles, which can cause significant delays in issuing subsequent instructions because the dependent instruction is stalled at the head of the issue queue.
To avoid some of these delays, some processor designs support the speculative execution of program code past the stalled instruction. Speculative execution involves executing instructions speculatively while preserving a pre-speculation architectural state of the processor. In these processors, the processor can discard speculative results and return to the pre-speculation architectural state if certain conditions occur during speculative execution (e.g., encountering an error/trap, a coherence violation, unavailability of processor hardware resources, executing certain types of instructions, etc.). However, if a speculative execution episode completes without encountering one of the conditions, the processor can commit the speculative results to the architectural state and continue with normal, non-speculative execution.
For example, some processors support an “execute-ahead” mode for speculatively executing instructions. In these processors, upon encountering an instruction with an unresolved data dependency while executing instructions in the non-speculative normal-execution mode, the processor defers the instruction by placing the instruction into a deferred queue and marking the destination register of the instruction “not-there” to indicate that the register is awaiting a result from a deferred instruction. The processor then transitions to the execute-ahead mode to speculatively execute subsequent instructions. During the execute-ahead mode, instructions with unresolved dependencies are deferred (and their destination registers are marked not-there), but instructions without unresolved data dependencies are executed in program order. In execute-ahead mode, instructions can be deferred if their source registers are not-there. However, these processors do not check the status of a source register until the processor is retrieving input operands in an execute unit while executing the instruction. In addition, as described above, the processor may automatically delay the issuance of an instruction for a given number of cycles to enable a prior instruction upon which the instruction depends to output a result to a destination register. Thus, an instruction that depends on prior instruction with an unresolved data dependency can be stalled at the head of the issue queue, awaiting the result of a prior instruction, despite the fact that the instruction is going to be deferred and will therefore not require the result of the prior instruction.